Data storage and processing apparatus, and method for fabricating the same

ABSTRACT

A data storage/processing apparatus includes ROM and/or WORM and/or REWRITEABLE memory modules and/or processing modules provided as a single main layer or multiple main layers on top of a substrate. Transistors and/or diodes operate the apparatus. In one set of embodiments, at least some of the transistors and/or diodes are provided on or in the substrate. In another set of embodiments, at least some of the layers on the top of the substrate include low-temperature compatible organic materials and/or low temperature compatible processes inorganic films, and the transistors and/or diodes need not be disposed on or in the substrate. In a related fabricating method, the memory and/or processing modules are provided on the substrate by depositing the layers in successive steps under thermal conditions that avoid subjecting an already-deposited, processed underlying layers to static or dynamic temperatures exceeding given stability limits, particularly with regard to organic materials.

This application is the national phase under 35 U.S.C. § 371 of PCTInternational Application No. PCT/NO99/00181 which has an Internationalfiling date of Jun. 2, 1999, which designated the United States ofAmerica.

The present invention concerns a data storage and data-processingapparatus, as well as a method for fabricating the same.

The invention particularly concerns a data storage and data-processingapparatus 3D scalable single- and multilayer memory and data-processingmodules and apparatus; and which even more particularly are based on ROMand/or WORM and/or REWRITABLE blocks addressed in a passive matrixscheme.

The present application claims priority from Norwegian PatentApplication No. 982518 titled “Scalable integrated data-processingdevice”, which has been assigned to the Assignee of the presentinvention and the disclosure of which is hereby additionallyincorporated by reference. This scalable integrated data-processingdevice, particularly a microcomputer, comprises a processing unit withone or more processors and a storage unit with one or more memories. Thedata-processing device is provided on a carrier substrate and comprisesmutually adjacent, substantially parallel layers stacked upon eachother. The processing unit and the storage unit are each provided in oneor more such layers and/or in layers formed with a selected number ofprocessors and memories in selected combinations.

In each layer are provided horizontal electrical conducting structureswhich constitute internal electrical connections in the layer andbesides each layer comprises further electrical conducting structureswhich provide electrical connections to other layers and to the exteriorof the data processing device. These further electrical structures in alayer are provided on at least a side edge of the layer as electricaledge connections and/or preferably as vertical conducting structureswhich form an electrical connection in a cross-direction of the layerand perpendicular to its plane to contact electrical conductingstructures in other layers.

In particular, the layers may be formed of a plurality of sublayers madeof organic thin-film materials. Some of all layers or sublayers may alsobe made with organic or inorganic thin-film materials or both.

A preferred embodiment of the data-processing device according to thepriority application is shown in FIG. 1. Advantageously are hereprocessors and memories, the latter, e.g., RAMs assigned to theprocessors, provided in one and the same layer. A processor interface 3with an I/O interface 8 is provided on a substrate S and above theprocessor interface 3 follows a processor layer P₁ with one or moreprocessors. Both the processor interface 3 and the processor layer P₁may as the lowermost layers in the data-processing device and adjacentto the substrate be realized in conventional, e.g., silicon-basedtechnologies.

Above the processor layer P₁ is provided a first memory layer M₁ whichmay be configured with one or more RAMs 6 assigned to the processors 5in the underlying processor layer P₁. In FIG. 1, however, the separateRAMs 6 in the memory layer M₁ are emphasized in particular. On the otherhand it is shown how the memories in the memory layer M₁ may be directlyconnected to the underlying processor layer P₁ via buses 7, the stackedconfiguration allowing such buses 7 to be provided in a large number bybeing realized as vertical conducting structures, while theconfiguration layer-on-layer allows for a large number of such busconnections being provided between the processor layer P₁ and the memorylayer M₁ and in addition with short signal paths. It will be realizedthat the juxtaposed arrangement in a surface would in contrast requirelonger connections and consequently longer transfer times.

Further, the data-processing device as shown comprises combined memoryand processor layers MP₁, MP₂, MP₃ provided with processors that areconnected mutually and to the processor interface 3 via the sameprocessor bus 4. All the combines memory and processor layers MPcomprises one or more processors 5 and one or more RAMs 6. Above thecombined memory and processor layers MP there is provided a memoryinterface 1 with an I/O interface 9 to external units and above thememory interface 1 follows memory layers M₂, M₃, . . . in as largenumber as desirable and possibly realized as the mass memory of thedata-processing device. These memory layers, M₂, M₃, etc. are in theirturn connected to the memory interface 1 via memory buses realized asvertical conducting structures 2 through the layers M₂, M₃, . . . .

The integrated data-processing device has a scalable architecture, suchthat, in principle, the device can be configured with an almostunlimited processor and memory capacity. In particular, thedata-processing device can be implemented in various forms of scalableparallel architectures integrated with optimal interconnectivity inthree dimensions.

In addition to comprising random accessible memories, the storage unitof the data-processing device can also comprise memories in the form ofROM, WORM or REWRITEABLE or combinations thereof.

The present invention particularly discloses how the three-dimensionalscalable single- and multilayer memory and data-processing modules maybe implemented with architectures and processing methods making themsuitable for application in a scalable integrated data-processing deviceof the above-mentioned kind, but not necessarily limited thereto.

BACKGROUND OF THE INVENTION

Advanced DRAM demonstration dies are presently available in 1-gigabit(Gbit) modules based on a 0.18 μm process over a 570 mm² chip area. Theconventional one-transistor DRAM cell requires roughly 10λ² area (whereλ is the minimum feature size) although processing “tricks” can reducethis significantly (40%). However row and column decode, drivers, senseamplifiers, and error correction logic cannot share the same siliconarea and account for a significant fraction of the DRAM die area. Moreimportantly, existing DRAM designs to date have not proven scalable to a3D stacked architecture. By their design, high density DRAM's are alsoinappropriate as ROM memories. The conventional NOR-gate based ROMrequires a nominal cell of 70λ² (though again reduced by processingtricks) limiting densities to <10⁸ bits/cm² under even the mostaggressive lithography assumptions. Higher densities can only beachieved through the use of both dense metal designs (minimum metalpitch) coupled with 3D integration. Technically and commercially viabledevices of this type have as yet not been forthcoming, although theenormous commercial potential has prompted a great deal of R&D effortsby the electronics industry, which in term has spawned a voluminouspatent literature.

3D Data Storage

Stacking of thin layers of memory on top of each other to achieve highvolumetric and areal densities has been attempted by using e.g. lift-offtechniques for inorganic thin film circuitry. However, the backgroundart has led to designs that have proven too complicated or costly tohave a commercial impact. In U.S. Pat. No. 5,375,085 “Three dimensionalferroelectric integrated circuit without insulation layer between memorylayers”, B. E. Gnade et al. have disclosed a layered, passivelyaddressed memory stack based on a ferroelectric memory substance.However, no concrete information is given, in particular relating toprocessability in multiple levels, showing how complete memory devicescan be made that include all the required ancillary active circuitry.Several patent applications involving stacking of thin film memorylayers etc. and which are of relevance for the present invention, havebeen filed by the present applicant. These include Norwegian patentapplications NO 973993, NO 980781, the above-mentioned NO 982518, NO980602 and NO 990867.

Dense Metal Designs

Passive matrix addressing provides a density corresponding to a unitcell area of approximately 4λ².

A number of patents exist where ROM devices employ passive matrixaddressing schemes, e.g.: U.S. Pat. No. 4,099,260 of D. N. Lynes et al.:“Bipolar read-only-memory unit having self-isolating bit-lines”; U.S.Pat. No. 4,400,713 of K. G. Bauge and P. B. Mollier: “Matrix array ofsemiconducting elements”; U.S. Pat. No. 5,170,227 of M. Kaneko and K.Noguchi: “Mask ROM having monocrystalline silicon conductors”; U.S. Pat.No. 5,464,989 of S. Mori et al.: “Mask ROM using tunnel currentdetection to store data and a method of manufacturing thereof”; U.S.Pat. No. 5,811,337 by J. Wen: “Method of fabricating a semiconductorread-only memory device for permanent storage of multilevel coded data”and PCT Pat. WO 96/41381 of F. Gonzalez et al.: “A stack/trench diodefor use with a multistate material in a non-volatile memory cell”.However, such schemes rely explicitly on traditional silicon waferprocessing, involving e.g. thermal treatment, implantation and etchingprocedures which are incompatible with the goals of the presentinvention, i.e.: low cost and optionally multilevel data storage.

The above-mentioned cited U.S. Pat. No. 5,375,085 discloses devicesbased on passive matrix addressing, but restricted to the special caseof ferroelectric memory materials. The ferroelectric materials referredas examples in that patent have, however, proven unsuitable in simplepassive matrix addressed memory schemes due to loss of polarization inunselected cells subjected to repeated partial switching. One- andtwo-transistor ferroelectric RAM (FERAM) devices avoid this problem, buthave not lent themselves to simple 3D scaling.

In U.S. Pat. No. 5,441,907 “Process for manufacturing a plug-diode maskROM”, H-C. Sung and L. Chen discloses a passive matrix addressed ROMwhere binary data are coded at each matrix crossing point by thepresence or absence of a diode connection. However, methods describingfabrication of devices according to the referred patent involve severalhigh temperature steps, include final annealing, which precludesconstruction of multilayers and the use of low-cost, low temperaturecompatible materials.

Thin Film ROM Devices

In GB Patent 2,066.566 “Amorphous diode and ROM or EEPROM deviceutilizing same”, S. H. Holmberg and R. A. Flasck discloses thin filmmemory devices based on fluorine-containing amorphous silicon. In U.S.Pat. No. 5,272,370 “Thin-film ROM devices and their manufacture”, I. D.French discloses a ROM device based on thin-film memory cells in apassive matrix addressing arrangement. Emphasis is explicitly onmultilevel (i.e. multi-bit) data storage in each memory cell, byproviding multilayer structures that can be individually selected foreach memory cell.

It is a main object of the present invention to provide architecturesand technical solutions where dense bit cell patterns in 2D can beincorporated into 3D storage structures, employing easily implementable,low-cost manufacturing technologies.

It is a further object of the present invention to provide ROM, WORM,and REWRITABLE memory devices with short random access times, high datatransfer rates and low power consumption. In the present document, theterm “REWRITABLE” shall be used in connection with memory cells whereinformation that has been stored can be exchanged by new informationthrough an erase/write or direct overwrite operation. Depending on theapplication, this operation may be performed only once, or repeatedly.

It is yet a further object of the present invention to provideintegrated data storage and processing devices where memory structuresand device architectures can be created in very dense structurescharacterized by short, highly parallelized interconnection paths in twoand three dimensions.

Finally, it is also an object of the invention to provide a fabricationmethod for a data storage and data-processing apparatus based onlow-temperature compatible processes and materials suited therefor.

The above-mentioned objects and advantages are realized by one or moreembodiments of the present invention. The objects of the presentinvention are particularly achieved by exploiting novel materials andprocesses that make possible the creation of devices with newarchitectures in two and three dimensions. Salient features in thatconnection are:

1) Memory modules are made by low-temperature compatible processes andmaterials i.e. polymers or low temperature processing of poly- or micro-or amorphous silicon. Low-temperature compatible in this context refersto processes not exceeding static temperatures compatible withpolymer-like substrates, or transient heating processes limited to timessufficiently short to be similarly compatible. As an example: In lasercrystallization of thin film silicon, the temperature in the outermostlayer is in fact quite high, but due to the short thermal pulse andtotal energy density, heat redistributes quickly into supporting layers.Beyond a certain depth, the latter do not reach high temperatures due tocalorimetric effects. For simplicity, low temperature compatibleprocesses and materials as described above may be referred to in thefollowing as “low temperature processing” and “low temperaturematerials”.

2) Low temperature processing makes possible the creation of memorymodules in one superlayer or a stack of superlayers without damagingunderlying circuitry nor other memory layers in the stack. This appliesboth to devices based on traditional single crystal silicon substrates,as well as plastic substrates with thin-film active circuitry. (In thelatter case, the short duration of the heat pulse typically used inlaser recrystallization appears to prevent damage to the plastic even attemperatures where a sustained thermal load would cause damage).

3) From 1) and 2) follow a number of beneficial consequences:

Possibility of stacked layers. Leads to:

High volumetric data density, and:

High density, short vertical interconnects, leading to high datathroughput:

Low capacitive and resistive interconnects due to short distance

high degree of parallelism (many vertical connections) for large wordwidths.

Exploiting areas in sublayer single crystal or high performancepolycrystalline, amorphous or microcrystalline layer underneath memorymodules for tasks requiring high-speed active circuitry. Examples:

Integrated SRAM data cache

Driver and interface electronics

On-board error detection and correction block-oriented circuitry toincrease reliability of memory layers

High area data density in each layer due to the passive matrixaddressing, with the option of locating driver circuitry layers belowand/or above as well as in the same layer.

Vertical interconnections can take many forms: One is penetratingconductors through vias, in which case the short distances and largeareas available in the stacked concept permit high data transfer speedsas mentioned above as well as flexible architectures, involving, e.g.staggered arrangement of vias as described in more detail in connectionwith a preferred embodiment below. Vertical interconnections can also beachieved by electrical conductors in each layer leading to the edge ofthe layer in question, where they are exposed and can be electricallyconnected to similarly exposed conductors in other layers. This may e.g.be facilitated by a step-wise extension of the edges of the lower-lyinglayers. Another class of vertical interconnections relies oncontact-less (non-galvanic) communication through the layers. This ispossible due to the layered architectures, i.e. capacitive, inductive oroptical coupling between circuits in different layers.

A preferred design according to the invention is realized as a layeredstructure built on a single crystal silicon substrate which contains allactive electronic circuitry. The latter communicates with one or moreoverlying memory layers through vias. Each memory layer containslow-temperature processed diode ROM and/or WORM and/or REWRITABLE arrayswhere high areal bit density is achieved through the use of passivematrix addressing. Each memory layer constitutes a self-contained entityand requires no high-temperature or chemically aggressive processingthat can damage the underlying structures during manufacture. Thus, thememory modules can be positioned on top of active electronic circuitryin the substrate, conserving substrate real estate and providing shortelectronic pathways between the active circuitry and the memory modules.Furthermore, memory capacity can be expanded by adding more memorylayers on top of the first, leading to a 3D stacked structure with veryhigh volumetric bit density.

Devices as described above lend themselves well to “back-end” processingof the memory modules, where all circuitry on the single crystal siliconsubstrate is first prepared using traditional silicon foundryprocessing. The subsequent deposition of the memory layer(s) may beperformed in a separate facility, e.g. if it is desirable to employmaterials and processes in this step which might represent acontamination problem for the silicon processing.

The driver and sense circuits are preferably fabricated in a standardCMOS process on single crystal silicon substrate to minimize costs andto achieve required high data transfer rates. The ROM/WORM/REWRITABLEarrays are then built above the final metallization layer coupled byvias to the underlying drivers. The diodes can be inorganic, e.g.amorphous, polycrystalline or microcrystalline silicon, or they can bebased on an organic material such as a conjugated polymer or oligomer.The passive matrix addressing scheme and the 3D architecture employingthe low temperature diodes provide a dramatic storage enhancement overall existing ROM/WORM/REWRITABLE designs, at only marginal cost abovethe underlying CMOS circuit.

For clarity and concreteness, a detailed description of the inventionshall be given below in terms of a preferred embodiment based onlow-temperature processed poly-Si diode ROM arrays in a stack with fourdouble-layer. The design can be easily extended for WORM memoriesapplications utilizing either induced explosive crystallization ofamorphous diodes or conductance modulation of interlayer organic films,and to REWRITABLE memories by incorporating highly functional memorymaterials in the memory matrices; cf. other patent applicationsbelonging to the present applicant, quoted in the present document.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description refers to the appended drawingfigures, of which

FIG. 1 shows an embodiment of a scalable integrated data-processingdevice to which the present invention may be applied,

FIG. 2 the schematic layout for a 1 GB ROM apparatus according to anembodiment of the present invention,

FIG. 3 the layout of the row/column addressing lines of a pair of memoryplanes of the ROM in FIG. 2,

FIG. 4 a staggered stacking arrangement of memory planes of the ROM inFIG. 2,

FIG. 5 a combination of several staggered stacking arrangements of thekind shown in FIG. 4 into a multisegmented staggered stackingarrangement of the memory planes of the ROM in FIG. 2,

FIG. 6 staggered vertical or horizontal vias for connecting through oracross memory planes and connecting the latter to underlying circuitry,

FIG. 7 a graph of the access time versus the number of memory blocksegments,

FIG. 8 a graph of the average addressing power requirement versus theaverage block (read) addressing size,

FIG. 9 vertical diodes in “on” and “off” memory element in a ROM, and

FIG. 10 vertical diodes as in FIG. 9, but fabricated by a self-aligningand -planarizing process.

DETAILED DESCRIPTION

The schematic layer layout for a 1 gigabyte (GB) apparatus according toan embodiment of the invention is shown in FIG. 2. Row demultiplexersand drivers, sense amplifiers, and column multiplexers are implementedin a conventional VLSI COMO single crystal chip forming the base of thestructure. All of the diode-ROM layers are fabricated after completionof the VLSI circuitry above a final dielectric deposition and CMPplanarization.

The details of the VLSI CMOS circuitry will not be discussed except asit specifically relates to the memory planes. The drivers and senseamplifiers are essentially identical to those used in conventional DRAMmodules and the designs can be lifted almost intact. Row driverinverters will have to be resized to accommodate the high capacitance ofthe diode-ROM configuration, and the sense amplifiers will need to bemodified for slower charging rates.

The memory planes are stacked layerwise and each ROM layer includessimple row/column line crossing linked potentially by a vertical diodestructure; a binary 0 (or 1) indicated by the presence of the diode. Atotal of eight memory planes, each incorporating 10⁹ bits, are requiredto yield the gigabyte module. To reduce the total number of mask levels,row lines are shared between two memory planes—reducing the speed, butsimplifying the overall fabrication.

The electrical schematic for each pair of memory planes is shown in FIG.3. Once a row address is latched (RAS), a final inverter drives one rowline to ground. Current flows through the diodes from the column lines(symmetrically from both column pairs) and the voltage drop on thecolumn line in sense in parallel for all column lines. Following read,the row line is returned to V_(DD) potential and the column lines totheir quiescent potential (between ground and V_(DD)-0.7). The power andspeed penalty for the diode defined memory (compared to a NOR MOSdesign) is more than offset by the density increase permitted by arow/column dense metal crossing layout. In a block-oriented data accessdevice, driving a single row inverter provides data readout for twocolumns. Although the speed of each row access may be limited bycapacitive charging, the total data transfer rate is “amplified” bytwice the column length. As discussed further below, the random dataaccess time can also be adjusted by appropriate segmentation of thememory, something which shall be discussed in more detail below withreference to FIG. 5.

Independent of the segmentation, the 3D memory layering requiresstaggered stacking of the memory planes on the Si die to provide areafor the row drivers, sense amplifiers, and peripherial circuitry. Thisstaggered stacking arrangement is shown in FIG. 4 wherein the memoryplanes are indicated by the light grey with single-crystal Si blocksdefined by darker grey. Each memory plane pairs is offset bothhorizontally and vertically to provide single-crystal silicon realestate for the row drivers (large inverters) and sense amplifiers. Allof the row drivers are fed from a common row decoder (NANDed with thefinal plane pair select) logic. The drawing is not to scale; inparticular the fraction of the area required for row drivers and senseamplifiers decreases roughly as the square root of the memory size.Sense amplifiers, assuming even a segmentation of 4096×4096 will occupyless than 10% of the die real-estate. For 256 Mbit arrays, this area isless than one percent of the total die.

In the stacked design with memory arrays above the single crystal logic,a significant fraction of the die remains unused. Some fraction of thisis required for bad-cell mapping and error-correction logic, but theremainder is preferred to be implemented as a SRAM data cache to reducemultiple accesses to the memory planes. As considered below, the primarypower dissipation occurs during memory access—reducing the numberrequired by resolving requests from cache has the potential todramatically reduce the overall power even in a random-access mode. Forrandom memory access, the cache would need to still provide some sort oflook-ahead predictive reads from memory to compensate for power andspeed limitations on direct access. For highly block-oriented memoryapplications, the cache becomes less critical and the area could insteadbe devoted to higher order error correction algorithms to improve dieyield and reduce costs.

Because of the capacitive loading from the diode elements, the optimalmemory structure of an 8-plane. 1 Gbit/plane, will not be 32.768×32.768arrays. Both the row line capacitance (from dielectric and diodeelements) and the column line capacitance increase linearly with thearray size. The row charge and diode current transfer set the powerdissipation; the column capacitance directly determines the chargeintegration time required for the sense amplifiers. To increase speed,the 1 Gbit memory blocks could be segmented as shown in FIG. 5, whereinthe stacked arrangement in FIG. 4 is used for combining several suchplanes alternating the sense of stacking between the separable blocks—atthe cost of increased driver electronics real-estate. But since largeareas of the Si substrate are unused in this design (remainder dedicatedto cache), this cost is not significant. The optimum segmentationdepends strongly on the application—in particular the averge size of thememory block accesses. In general, smaller segments are essential, forpower dissipation reasons, as the block size drops. Minimum randomaccess speed can also be dramatically improved by increasing the numberof memory segments. (Both of these issues are considered further below.)

It is also possible to implement the multiple array blocks using only asingle pair of sense amplifiers using common column vias with diodeisolation between the planes. However, there is a severe speed penaltyin this design due to the time required to turn-on the isolation diodefor the planes. In the futures when active MOS isolation transistors areviable on the memory planes single sense amplifier designs can beutilized for some applications. But the die size gains are minimal sincethe underlying substrate is not real-estate limited.

To achieve required data transfer rates, all of the sense amplifiersmust be latched during data strobe providing a block transfer to thecolumn decode logic. This would naturally occur within a SRAM cache aspart of the design. Assuming a CD-ROM based replacement, the majority ofdata accesses will be resolved from the column latch cache withoutadditional row data strobes.

Limitations arising from dense vias between device level and the uppermemory blocks could be of concern, but this is not the case since thevias can be staggered satisfying both design rules for conventional viaattach and achieving dense metal wiring density for the memory arrays.Simple staggering of the vias, as shown in FIG. 6, illustrates onepossible solution. Vias are staggered up (or across) the die torigorously satisfy the 2×2λ via size, 1λ metal overlap on all sides ofthe via. 3λ minimum via spacing, yet maintaining wiring at full densemetal within the memory array itself. The vias will generally beseparated further than illustrated to accommodate the actual requiredspace of the sense amplifier or row drivers. In this layout, one line inN is lost. To maintain uniform metal density and optimize processdevelopment (necessary to push metal pitch beyond random logic designrules), the missing line is replaced with a dummy metal line (noconnection). The reduced row/column density arising from this staggerapproach is incorporated in calculation results given in the designanalysis below. Although illustrated for a 2λ via, the extension to anarbitrary size via for connecting memory arrays to Metal 1 or 2 isobvious.

With the general layout defined as above, the required die size can nowbe determined. The memory plane density is limited by memory metalwiring pitch and sets the overall density of the memory. A conservativedesign requires metal pitch based on both minimum via overlap andmetal-to-metal spacing. The overall die size will then be roughly 20%larger than the memory plane itself (for staggered layout andperipherial drivers). However, it is not necessary to limit metal torandom logic design limitations. By moving to a full dense metal arraywith uniform spacing and density, the line width and spacing can bereduced considerably. As long as random wiring is minimized on thememory planes, lithography and etching can be specifically optimized tothe dense metal pitch allowing use of poly or metal 1 line widths evenin these upper layers. This cannot apply to the vias—but as shown abovethese are fabricated well within the design rule limits.

In addition, the simple design of the memory cell does not require viametal overlap within the memory cell; lithography misalignments mayreduce the contact area (one axis), but the subsequent interlayerdielectric will passivate the exposed diode component. These two processmodifications allow the maximum metal pitch resulting in the 4λ² cellareas (where λ is approximately the metal width/spacing).

Table 1 fully compares three technologies based on 0.35, 0.25, and 0.18μm lithography (design rules taken from both TSMC and MOSIS scalabledesigns). The table below summarizes results for a 1 GB design assuming512 byte average block transfers and a design requirement for 1000 MB/stotal data transfer. The segmentation is the recommended size to balanceaccess times, with a 100 ns maximum requirement.

TABLE 1 0.35 μm 0.25 μm 0.18 μm Via size/spacing 0.50/0.45 0.36/0.380.24/0.28 Metal width/spacing 0.60/0.50 0.40/0.40 0.28/0.28 Metal viaoverlap 0.20 0.15 0.10 Dense metal (cells) width 0.40 0.30 0.24 Densemetal (cells) 0.40 0.30 0.24 spacing Minimum cell size 0.8 × 0.8 μm 0.6× 0.6 μm 0.48 × 0.48 μm Cell area 0.64 μm² 0.36 μm² 0.23 μm² MemoryDensity/ 0.156 Gb/cm² 0.278 Gb/cm² 0.435 Gb/cm² Layer OptimalSegmentation 16 4 4 (#) Die area 742 mm² 402 mm² 257 mm² Random AccessTime 52 ns 76 ns 68 ns Power dissipation 25 mW 22 mW 9 mW (array)

It is thus feasible to implement a 1 GB memory in existing 0.25 μmtechnologies—with a die size well within reasonable constraints (<500mm²). For 0.35 μm design rules, the single chip die size is probably toolarge to be manufacturable, but a 0.5 GB array is within reason. Theonly caveat on 0.35 μm technology is that the upper level metalplanarization must be implemented as a CMP process to provide theplanarity required for dense metal on upper layers.

Memory speed and power dissipation shall now be considered in relationto design and operating parameters.

Design parameters: For the purposes of this design example, thefollowing approximations were used:

Row and column line parasitic capacitances will taken as equal to thedirect capacitance

Interlayer dielectric is 300 nm of SiO₂ equivalent

Metal line conductivities are 0.07 Ω/□

Sense amplifier minimum threshold is 10 mV

Diode transconductance is 10³ A/cm² for a 1 V forward bias

Diodes are one-sided junction with 400 nm depletion width at zero bias(10¹⁷ doping)

Data Transfer Rate

The desired 1 Gbit/s sustained data transfer rate is easily achievedonce the column latches are filled. Even in a 4096 segmentation, eachrow access satisfies 8192 latches requiring row read times of only 10μs, whereas actual data access times are sub 1 μs. However, this assumesthe data transfer is highly correlated and all 8192 column bits areuseful. The penalty arises in power as this is violated.

Access Time

The instantaneous data access speed (time from RAS to data available onCAS latches) is determined by the charge time through the diodes to thecolumn line capacitance. This will be the more difficult parameter toachieve within a diode-based ROM cell. The time is a complex function ofthe array size (segmentation), diode conductance, diode capacitance(major), row drive line resistance and sense amplifier minimum voltagesensitivity.

The access time is the sum of the row charge time (R_(row)C_(row)), thecolumn sense integration time to the minimum specified voltage swing(C_(col)ΔV/1_(diode)), and an estimate of random logic delays forrow/column addressing.

As evinced by the graph of FIG. 7, the access speed is only slightlydependent on the lithography rules, but strongly depends on thesegmentation size. There are decreasing returns above 16 segments forthe array.

Power Dissipation

The primary design parameter influencing the power dissipation is theaverage size of the block transferred in each read. As long as the readrequest can be resolved out of the row read cache, the power requiredfor charge and sense amplifiers can be averaged over a large number ofread cycles. But if the access becomes random requiring a row chargecycle for every access, the power requirement will grow substantially.The graph of FIG. 8 illustrates the estimated power requirement as afunction of the average block read size with a sustained data transferrate of 1000 GB/s. For this purpose, the four-segmented 0.25 μm designwas used. Note that the scale are logarithmic. As long as the averageblock size remains above a few hundred, the power dissipation isdetermined by the intrinsic transfers. As the size drops though,additional row reads are required and the power rises inversely with theblock size.

Memory Plane Fabrication

The multiple plane implementation of an e.g. ROM memory according to thepresent invention requires that upper level processing retain planarstructures with minimal topography growth (over 12 metal layers).Processing must be consistent with metal line exposure on row/columnvias—effectively limiting processing to <250° C. Preferably, thefabrication of the diodes shall also be self-aligning with the contactvias to reduce mask count.

Two feasible routes shall now be discussed, based on inorganicsemiconducting materials:

microcrystalline Si selectively deposited on a metal/Si seed layerthrough vias (or blanket deposition and CMP etch).

explosive crystallization of blanket a-Si—leaving high resistivity a-Sifor planarization—using laser intensity modulation with the viadielectric.

Memory density at 4 f² requires the isolation diodes to be fullyprocessed and contacted in a vertical configuration—in contrast to thetraditional planar configuration present in today's technology. Theisolation diodes in either a ROM or impedance controlled RAM devices arefabricated directly on the row/column metal as indicated in FIG. 9. Thememory cell on the left, for a ROM, is “on” while the memory cell on theright remains off. In the simplest configuration, the only differencebetween memory cells is the presence or absence of a cut in theinterlayer dielectric patterned over the diode material. Severalspecific fabrication technologies will be discussed, beginning from themost complex using present manufacturing technology to those involvingonly more esoteric processes.

The fabrication of vertical diodes by directed energy processing shallnow be discussed with reference to specific processing examples.

Example A Fabricating Diodes Directly on Metallization with Polymer/lowTemperature Substrates

Common to all fabrication strategies is the formation of a p-n junctiondiode in the vertical orientation directly on the dense metal line arrayforming the row or column lines of the memory. Transient thermalprocessing, specifically pulsed laser or ion beam, is the preferredmethod for fabrication as it is compatible with other low temperaturematerials for WORM/RAM applications. The method involves:

i. Deposition of metal film for row/column underlying matrix. The choiceof the underlying metal depends in part on the method below, asdiscussed further below. The metal film may be a multilayer consistingof a highly conductive underlayer (Al) and an interface barrier forcontact with the Si (eg. tungsten).

ii. Deposition of thin amorphous donor (n-type) doped silicon by, forexample, sputtering, e-beam evaporation or PECVD.

iii. Deposition of a second layer, in-situ, of acceptor (p-type) dopedsilicon or germanium.

iv. Laser-induced crystallization of the amorphous films formingpolycrystalline pn junction diodes. The energy density is chosen toachieve full or nearly full melt of the silicon film resulting innucleation from the metal layer. This will result in large grain (>50nm) polycrystalline diodes with the junction near the original p-ndeposition boundary.

v. Mask and etch of the lower level row lines, followed by conformaldeposition of interlayer dielectric (SiO₂).

vi. Patterning of contact level defining “on” and “off” memory cells.

vii. Column metal deposition and pattern/etch.

Example B Modification to Utilize Explosive Crystallization

The fluence required for crystallization in (iv) above is determined bythe film thickness. The crystallization may alternatively be done usingthe explosive crystallization (M. O. Thompson, Phys. Rev. Lett. 52:2360(1984) method requiring only the formation of a minimal surface melt.The enthalpy difference between the amorphous and crystal phases willdrive the melt through the film with minimal net thermal impact on thelower metal layer. The resulting diode layer is a mixedamorphous/polycrystalline phase but retains sufficient current density(100 A/cm²) for memory isolation applications.

Example C Modification to Use Schottky Diodes

Instead of deposition p and n films for a junction diode, the processmay be modified to fabricate Schottky barrier diodes directly with thelower metal film. This modification involves the deposition of only ann-type film, crystallization and formation of a Schottky barrier witheither the direct metal (minimal liquid interaction) or with a silicidephase formed iva partial melting of the metal contact. This modificationis most appropriate with explosive crystallization to minimize thethermal energy dissipated in the metal layer.

Example D Modification to Auto-dope from the Metal Contact

Electrically active dopants can be incorporated into the metal filmeliminating the need for separate films of n and p type Si (steps ii andiii above). A thin coating of arsenic or boron on a tungstenmetallization, or an alloy containing boron or arsenic, can providecompensating doping to a single film deposition. The partial melting andincorporation of the impurities from the metal or metal overcoat,followed by liquid-phase diffusion and potentially segregation duringcrystallization, will form a p-n junction as well. The position of theinterface is controlled by the crystallization dynamics and can becontrolled by fluence modification, again primarily in the explosivecrystallization regime.

Example E Modification to Use Germanium

All of the above methods work equally well with germanium as forsilicon. Although germanium polycrystalline diodes may show higherleakage, this is offset by the 450 K reduction in all of the liquidprocess temperatures. Although transient, the molten phase isnevertheless extremely reactive.

Example F Metal Selection

Aside from the modification disclosed as example C above, the primaryrequirement for the metal is to minimize interactions with the moltensemiconductor during solidification. Candidate metals then include therefractory metals such as tantalum, tungsten, and platinum,mid-transition metals including Pd, Mo, Ni, Co or Cr, current diffusionbarriers such as TiN, and terminal silicide phases such as NiSi₂. All ofelemental metals form stable silicide phases and moderate reaction isexpected with the liquid Si or Ge. Use of a stable silicide wouldminimize such reactions; however, since the silicides are adequateconductors as well, formation of a thin silicide is generally not aproblem. Formation of a well-defined silicide is required forimplementation of the modification given as example C.

For self-alignment and planarization of the diodes certain processingmay be introduced.

The process described in example A above is conventional semiconductorprocessing involving accurate overlay of the contact mask withunderlying row metallization. In addition, the etch processes produceincreasing rough topologies that must be planarized for stacked 3Dintegration. However, the 10³-10⁵ difference in conductivity betweenpolycrystalline and amorphous phase can be used to develop self-aligningdiode definition patterns and simultaneously address planarizationissues. The primary modification for this mode is to leave amorphousphase material in the inter-diode regions and minimize the featureheights. The process flow in this case would be:

i. Deposition and patterning of the metal for row lines. This would befully etched and planarized with dielectric between metal lines.

ii. Uniform deposition of n and p amorphous films (or single layer viamodifications discussed above).

iii. Deposition of contact dielectric plus thin metal reflector layer(Cr or Al). Pattern etched leaving vias where diodes are to be formed.

iv. Laser irradiation through the patterned film. Only in the vias willsufficient energy be absorbed to initiate crystallization of the silicon(explosive or full melt).

v. Metal deposition for the column lines. (The reflector film, if ofcompatible metal, need not be removed prior to deposition—it can beetched simultaneously). Column lines patterned and etched.

vi. Dielectric deposition and planarization.

In this process, the alignment of column metal with alignment vias isrelaxed. Misalignment cannot result in short-circuiting of column to rowsince the underlying metal is fully coated with amorphous silicon. Theconductivity of the amorphous Si must be maintained sufficiently lowthat crosstalk between row lines is insignificant. This is easilyachieved using very lightly doped a-Si films with the diode formed byincorporation of dopants from the underlying metallization (Example Dabove).—For the resulting diode structure, reference may be made to FIG.10.

In another modification, a long wavelength laser is used to initiatecrystallization rather than using a short wavelength (excimer laser) asthe irradiation source. At 1.06 μm (the Nd:YAG wavelength), amorphous Siis sufficiently transparent that the energy can be transmitted throughthe amorphous film and absorbed only by the underlying metal film. Thismetal then initiates the explosive crystallization (or full melt). Theadvantage of this mode is that the diodes are formed only in the rowmetal region.

Finally the diode arrays can be patterned using a patterned laser beam(imaging through a mask) instead of using the on-wafer pattern. This islimited to larger feature sizes (1 μm) but eliminate severalphotolithography steps.

The present invention is by no means limited to ROM devices, but may beimplemented as various kinds of memory and data processing apparatus andmodules, as mentioned in the introduction. A brief discussion ofalternative preferred embodiments shall now be given.

The basic architectures described above can also be adapted for WORMapplications. This is achieved by starting out with passive matrixarrays where all crossing points exhibit rectifying diode behaviorinitially. Writing to a given crossing point is achieved by creating anopen circuit, i.e. destroying the forward conductance of the diode.

In one class of embodiments, the matrix array is made by sandwiching aconjugated polymer between the two sets of parallel electrodes thatconstitute the passive matrix, with electrode and sandwich materialsselected so as to create spontaneously a rectifying diode at eachcrossing point. The associated physics has been thoroughly investigatedand described in the scientific literature. Writing to a given crossingpoint is achieved by one of several methods. The most straightforwardone, but not the only one, is to create thermal damage by a short butintense current pulse through the polymer material at the crossingpoint, causing a spatially controlled reduction of the conductance, oran open circuit. Descriptions of suitable materials and geometries havebeen given in the following patent applications controlled by thepresent applicant: Norwegian patent applications NO972803 and NO973390and applications derived therefrom.

While reading is performed at low bias in close analogy to the preferredembodiment discussed under Section 4 above, writing requires highercurrents and a different pulsing protocol. Thus, the temporal profile ofthe energy dissipation at the crossing point must be closely controlledin order to obtain the required thermal history at the diode junction,as well as confining the region of current-induced impedance change(e.g.: thermal damage) to the crossing point being written. Theseaspects imply that the electronic complexity is higher for a WORM memoryas compared to the ROM type, and this taken together with the highercurrent requirements during writing lead to somewhat lower bitdensities. On the other hand, the all-electronic writing process impliesthat the foundry-based processing steps involved in manufacturing, e.g.masked ROMs are avoided.

As is readily apparent to a person skilled in the art, the basicarchitectures described above open up opportunities for integrating ROM,WORM and REWRITABLE arrays in a single device, either in the same layeror layers, or as separate ROM, WORM and REWRITABLE layers in a singlestack. Among the many possibilities resulting from this, combiningmemory types of this kind, shall particularly be mentioned.

Yield Enhancement by Self-diagnostics

As part of the post-manufacturing testing and qualification procedures,a self-diagnosis program in the ROM is activated to identify faults inthe memory. Results are stored in the WORM and linked to instructionsderived from the ROM, causing faults in the memory device to becircumvented or corrected. This is implemented in a fashion which istransparent to the user, apart from a possible latency. In this manner,the manufacturing yield can be enhanced.

A direct extension of the above-mentioned devices which may or may notcombine different types of memory is to include processing power intothe 2- and 3-dimensional architectures. Thus, distributed processors(including but not limited to microprocessors) with fast and directaccess to dedicated memories in close physical proximity shall provideprovide speed and flexibility not attainable by processor/microprocessorarchitectures based on traditional silicon wafer technology. For a morethorough discussion of these and related themes, particularly integratedmemory and processing structures in a scalable architecture, referencemay be made to Norwegian patent application NO 982518, wherefrom thepresent application derives priority and the computer literature ingeneral.

As is apparent, the present invention provides extension of the ideasand concrete embodiments in the above mentioned literature, throughnovel architectural solutions as well as through the use of materialsand processes that facilitate implementation of high density 2- and 3-Dstructures.

What is claimed is:
 1. A data storage and processing apparatus comprising: ROM and/or WORM and/or REWRITABLE memory modules on a substrate; and/or one or more processing modules on the substrate, wherein the memory and/or processing modules are provided as a plurality of main layers formed vertically on top of the substrate, wherein each main layer of a memory module and/or processing module comprise functional sublayers, wherein the memory modules and/or processing modules in each main layer communicate through vias, surface or edge connections with other main layers and with circuitry provided on or in the substrate and wherein the apparatus comprises active components in the form of transistors and/or diodes for operating the apparatus, characterized in that at least some and at most all the transistors and/or diodes for operating the apparatus are provided on or in the substrate, and wherein each main layer comprises a combination of organic materials and inorganic materials.
 2. Apparatus according to claim 1, characterized in that at least a portion of the substrate contains semiconducting materials in doped or undoped form provided in bulk or as thin film on a passive carrier, and where the semiconducting materials are selected from one or more of the following, viz. silicon, gallium arsenide and germanium in amorphous, polycrystalline, microcrystalline, bulk or process-defined single crystal form, or organic semiconducting materials including molecules, oligomers or polymers or combinations thereof.
 3. Apparatus according to claim 1, characterized in that the circuitry provided on or in the substrate is realized by one or more of the following technologies, viz. CMOS, NMOS or PMOS.
 4. Apparatus according to claim 1, characterized in that the circuitry provided on or in the substrate comprises one or more cache memories in the form of SRAM, DRAM and/or ferroelectric RAM (FERAM).
 5. Apparatus according to claim 1, characterized in that it comprises thin-film circuitry.
 6. Apparatus according to claim 1, characterized in that the circuitry provided on or in the substrate comprises processors for detection and correction on memory errors and defects.
 7. Apparatus according to claim 1, characterized in that the circuitry provided on or in the substrate comprises processors for remapping defect memory regions in the overlying layers and/or the substrate.
 8. Apparatus according to claim 1, characterized in that the circuitry provided on or in the substrate comprises processors for dynamically remapping the memory modules in order to optimize performance and lifetimes thereof.
 9. A data storage and processing apparatus, comprising: a substrate including an active circuitry, wherein the active circuitry includes at least one of one or more transistors and one or more diodes for operating the apparatus; and a plurality of main layers above the substrate, wherein each main layer includes at least one of one or more memory modules and one or more processing modules; wherein: the memory and processing modules within each main layer communicate with memory and processing modules of other layers and with the active circuitry of the substrate through at least one of vias, surface connections, and edge connections of each main layer; and each main layer includes a stack of one or more functional sublayers, with each functional sublayer realizing one or more specific circuit functions, wherein each functional sublayer comprises a combination of low temperature-compatible organic thin-film materials and low temperature-compatible processed inorganic thin-film materials, and wherein each main layer includes a portion of the active circuitry.
 10. The apparatus according to claim 9, wherein at least one of the main layers comprises memory modules with passive matrix-addressable memory elements defined in a memory material at crossings between electrodes of a first set of parallel electrodes provided on a surface of the memory material and a second set of parallel electrodes provided on an opposite surface of the memory material and in intersecting relationship with the first set of electrodes, the memory elements being realized as non-linear impedance elements at the crossings, and each memory element is provided with a logic value given by an electrical impedance.
 11. The apparatus according to claim 10, wherein each non-linear impedance element is one of a rectifying diode and a thin-film transistor.
 12. The apparatus according to claim 11, wherein the non-linear impedance elements are made of at least one of the following: at least one of silicon, gallium arsenide and germanium in at least one of the forms of amorphous, polycrystalline, microcrystalline, bulk, and process-defined single crystal; and organic semiconducting materials including at least one of molecules, oligomers, and polymers, and combinations thereof.
 13. The apparatus according to claim 10, wherein at least one main layer comprises dual passive matrix-addressable memory modules in separate sublayers, one overlying and one underlying memory module sharing one set of row or column electrodes.
 14. The apparatus according to claim 10, wherein a plurality of main layers is provided and wherein at least two of the main layers share at least one of common row and column drive electronics and share optional sense electronics connected therewith through common wires.
 15. The apparatus according to claim 9, wherein a plurality of main layers is provided, wherein each main layer includes a plurality of memory modules, the memory modules being in the form of juxtaposed segments stacked on the top of other juxtaposed segments in the main layer to form two or more juxtaposed stacks on the substrate, and that a part of each segment in each stack is connected to a portion of the substrate and communicates electrically with the active circuitry provided thereon.
 16. The apparatus according to claim 9, wherein a plurality of main layers is provided, wherein each main layer includes a plurality of memory modules, the memory modules being provided in the form of juxtaposed segments stacked on the top of other juxtaposed segments in the main layer in a staggered arrangement such that each memory module in the stack is provided staggered in relation to adjacent neighbor modules, and that a part of each segment in each stack is connected to a portion of the substrate and communicates electrically with the active circuitry provided thereon.
 17. The apparatus according to claim 9, wherein a plurality of throughgoing electrical conductors or vias providing power and signal connections among the main layers and the substrate is distributed laterally in a staggered arrangement.
 18. The apparatus according to claim 9, wherein each memory module is one of a ROM, a WORM, and a REWRITEABLE type.
 19. The apparatus according to claim 18, wherein at least one memory is one of a masked ROM and a patterned ROM.
 20. The apparatus according to claim 9, wherein at least one main layer includes memory modules of at least two of the ROM, WORM, and REWRITEABLE types.
 21. The apparatus according to claim 9, wherein at least a portion of the substrate comprises circuitry which is electrically connected with one or more of the main layers.
 22. The apparatus according to claim 21, wherein the active circuitry of the substrate is formed from one of doped and undoped semiconducting materials on a passive carrier in one of bulk and thin film form.
 23. The apparatus of claim 21, wherein the semiconducting materials are selected from at least one of: at least one of silicon, gallium arsenide and germanium in at least one of the forms of amorphous, polycrystalline, microcrystalline, bulk, and process-defined single crystal; and organic semiconducting materials including at least one of molecules, oligomers, and polymers, and combinations thereof.
 24. The apparatus according to claim 22, wherein the active circuitry is realized by one or more of CMOS, NMOS, and PMOS technologies.
 25. The apparatus according to claim 22, wherein the active circuitry includes one or more cache memories in the form of at least one of SRAM, DRAM and ferroelectric RAM (FERAM).
 26. The apparatus according to claim 22, wherein the active circuitry includes processors for detection and correction of errors and defects of the memory modules.
 27. The apparatus according to claim 22, wherein the active circuitry includes processors for remapping defective memory modules.
 28. The apparatus according to claim 22, wherein the active circuitry includes processors for dynamically remapping memory modules.
 29. The apparatus according to claim 9, wherein the inorganic thin-film material is at least one of silicon, silicon compounds, metals, metal compounds, and any combination thereof.
 30. The apparatus according to claim 9, wherein the active circuitry of the main layers is realized in thin-film technology.
 31. A method for fabricating a data storage and processing apparatus including a substrate including an active circuitry, wherein the active circuitry includes at least one of one or more transistors and one or more diodes for operating the apparatus, and the apparatus also including one or more main layers above the substrate, wherein each main layer includes at least one of one or more memory modules and one or more processing modules, wherein the memory and processing modules within each main layer communicate with memory and processing modules of other layers and with the active circuitry of the substrate through at least one of vias, surface connections, and edge connections of each main layer; wherein each main layer includes a stack of one or more functional sublayers, with each functional sublayer realizing one or more specific circuit functions, wherein each function sublayer comprises a combination of low temperature-compatible organic thin-film materials and low temperature-compatible processes inorganic thin-film materials; and wherein each main layer includes a portion of the active circuitry, the method comprising: depositing and processing the main layers and functional sublayers of each main layer thereof in successive steps, wherein: the depositing step includes one or more of: selecting from semiconductor materials among thin films of amorphous, polycrystalline or microcrystalline silicon or germanium, oxides, dielectric materials, metals or combinations thereof and depositing the layer of such material by one of sputtering, evaporation, chemical vapour deposition or plasma-assisted chemical vapour deposition, spin coating, and combinations thereof; and selecting from polymer materials among molecular, oligomer, and polymer and depositing the layer of such material by one of solvent techniques, evaporation, sputtering, vacuum-based techniques, film transfer techniques, and combinations thereof; and the processing step includes one or more of: processing each deposited layer of semiconductor materials using one of photolithography, wet etching, dry etching, reactive ion etching, plasma etching, chemo-mechanical polishing, ion implantation, and combinations thereof; and processing each deposited layer of polymer materials using transient heating with one of pulsed laser or particle beams for inducing crystallization of deposited amorphous films, grain refinement of deposited films, and incorporation and activation of dopants therein, wherein; the deposited layer is processed under thermal conditions that avoid subjecting an already deposited and processed layer to a static temperature exceeding a temperature in a range of 150-450° C.; and the deposited layer is processed under thermal conditions that avoid subjecting an already deposited and processed layer to dynamic temperatures exceeding a transient stability limit of the polymer materials, wherein the transient stability limit is defined as one of being less than 500° C. for not more than 10 ms and process-induced chemical damage.
 32. The method according to claim 31, wherein fabricating a thin-film silicon-based circuitry and transistors is performed by a low-temperature compatible process using laser-induced crystallization and dopant activation of the thin-film transistors.
 33. The method according to claim 31, wherein a memory module is realized as a matrix-addressable memory with isolation diodes, characterized by forming isolation diodes in one of vertical and planar configurations by depositing directly amorphous at least one of microcrystalline and polycrystallines n- and p-type silicon or germanium films and depositing directly semiconducting organic thin films of oligomer or polymer.
 34. The method according to claim 31, wherein a memory module is realized as a matrix-addressable memory with isolation diodes, characterized by forming the isolation diodes by laser-induced melting and solidification of deposited n- and p-type amorphous or microcrystalline films of inorganic semiconducting material directly on underlying one or more low temperature-compatible layers.
 35. The method according to claim 34, characterized by protecting the one or more underlying layers from reacting with molten semi conductor material during the laser-induced crystallization by providing a thin-film diffusion barrier.
 36. The method according to claim 34, characterized by designing a reaction between a molten semiconductor material and the one or more underlying layers to form a stable electrical conducting compound.
 37. The method according to claim 31, wherein a memory module is realized as a matrix-addressable memory with isolation diodes, characterized by: forming the isolation diodes by laser-induced melting and solidification of deposited amorphous or microcrystalline inorganic film; and forming a pn junction of the diodes with compensating doping, the pn junctions being realized either from one of a deposited layer on an underlying metallization and autodoping using alloying elements in a passive matrix metallization.
 38. The method according to claim 31, wherein a memory module is realized as a matrix-addressable memory with isolation diodes, characterized by: forming the isolation diodes by laser-induced melting and solidification of a deposited amorphous or microcrystalline inorganic film; and forming a Schottky-barrier diode with one of an underlying metallization structure and a compound formed by a reaction with the underlying metallization structure.
 39. The method according to claim 31, characterized by: constraining the laser-induced crystallization within an explosive crystallization regime; transient melting of the surface of the film; forming self-propagating liquid film.
 40. The method according to claim 31, characterized by forming isolating structures from high resistivity or anisotropic contact materials.
 41. The method according to claim 40, characterized by inducing modification of the contact materials by one of chemical and thermal techniques to thereby realize both the isolation diode and the non-conductive interlayer dielectric.
 42. The method according to claim 41, characterized by the chemically or thermally induced modification taking place respectively by autodoping of high-resistivity amorphous silicon and laser-induced crystallization of high resistivity amorphous silicon.
 43. The method according to claim 31, wherein a memory module is realized as a matrix-addressable memory with isolation diodes, characterized by: forming diodes in spatially limited regions, wherein the limited regions include intersections of the matrix and simultaneously providing lateral isolation between the diodes by using a self-aligned process; limiting the formation of diode junctions to the spatially limited regions by one of laser-induced crystallization with modulation of absorbed laser energy by features of underlying layers or structures, laser-induced crystallization with modulation of absorbed laser energy by antireflective or reflective thin films, constraining nucleation during laser-induced crystallization to metal regions by controlling an interlayer dielectric surface, using underlying layers or structures as dopant sources for diode junction formation via explosive crystallization, and selective chemical or physical vapour deposition of amorphous or microcrystalline films effected by surface modification of an interlayer dielectric surface.
 44. The method according to claim 31, characterized by separating the functional sublayers with planarized dielectric layers, wherein the dielectric layers are made of at least one of oligomer, polymer, and inorganic material.
 45. The method according to claim 31, characterized by initiating the induced crystallization by directed energy sources other than lasers, including pulsed ion and electron beams.
 46. A data storage and processing apparatus, comprising: a substrate including an active circuitry, wherein the active circuitry includes at least one of one or more transistors and one or more diodes for operating the apparatus; and one or more groups of memory planes, wherein each group includes a plurality of memory planes formed above the substrate, wherein for each group: the plurality of memory planes are stacked, a memory plane of the plurality is displaced in an X direction or Y direction or both in relation to another memory plane of the plurality, and each memory plane of the plurality is configured to electrically communicate with the active circuitry of the substrate.
 47. The apparatus according to claim 46, wherein: the apparatus includes a plurality of groups of memory planes; and each group is juxtaposed in relation to another group above the substrate.
 48. The apparatus according to claim 47, wherein the memory planes electrically communicate with the active circuitry through at least one of vias, surface connections, and edge connections.
 49. The apparatus according to claim 47, wherein the memory planes are formed from a combination of low temperature-compatible organic thin-film materials and low temperature-compatible processed inorganic thin-film materials, and wherein each main layer includes a portion of the active circuitry. 